XDA Developers on MSN

5 problems you didn't know a CMOS reset could fix

Discover how a simple CMOS reset can resolve common PC hardware problems like black screen, bad overclocks, undervolting, ...
EDN

2 MBit CMOS Memory FRAM Chip

The MB85R2001 is 2 Mbit Ferroelectric Random Access Memory (FRAM) chip packaged on a 48-pin plastic TSOP and operating at a temperature range of -20°C to +85°C. It has 10 years of data retention and ...
Automation World

Scalable, Printed CMOS Memory Enables Internet of Things

Practically since its founding over eight years ago, Automation World has covered the technology and applications of the connected world, now dubbed the “Internet of Things.” The most recent example ...
Electronic Design

CMOS Memory Includes MTP Fuse

The AEFuse embedded, nonvolatile memory cores include what is said to be the first multiple-times-programmable (MTP) fuse fabricated in standard 0.25 µm and 0.18 µm CMOS processes. Offered as a ...
EDN

Hybrid system resolves edge AI’s on-chip memory conundrum

A hybrid memory system combines the best traits of ferroelectric capacitors and memristors in a single memory stack.
Semiconductor Engineering

Research Bits: Sept. 30

Researchers from Massachusetts Institute of Technology (MIT) and University of Chemistry and Technology Prague created a ...
DATAQUEST

French team led by CEA-Leti develops first hybrid memory tech enabling on-chip AI learning and inference

Project demonstrated that it is possible to perform on-chip training with competitive accuracy, sidestepping the need for off ...

Micron says HBM4 customer samples are now shipping with bandwidth above 2.8TB/s and pin speeds exceeding 11Gbps

Micron announces industry leading HBM4 with 2.8TB/s bandwidth and 11Gbps pin speeds, claiming performance advantage over ...
Electronic Design

64-MBit Parallel Flash Memory Device Leverages CMOS SuperFlash

A 4M x16 CMOS Advanced Multi-Purpose Flash Plus (Advanced MPF+), dubbed the SST38VF6401B by Microchip, takes advantage of the company’s CMOS SuperFlash technology—a split-gate cell design and ...
Semiconductor Engineering

CMOS-Based HW Topology For Single-Cycle In-Memory XOR/XNOR Operations

A technical paper titled “CMOS-based Single-Cycle In-Memory XOR/XNOR” was published by researchers at University of Tennessee, University of Virginia, and Oak Ridge National Laboratory (ORNL). “Big ...
Science Daily

Demonstration of high-speed SOT-MRAM memory cell compatible with 300mm Si CMOS technology

Researchers have announced the demonstration of high-speed spin-orbit-torque magnetoresistive random access memory cell compatible with 300 mm Si CMOS technology. Researchers at Tohoku University have ...
EurekAlert!

Demonstration of high-speed SOT-MRAM memory cell compatible with 300mm Si CMOS technology

Researchers at Tohoku University have announced the demonstration of high-speed spin-orbit-torque (SOT) magnetoresistive random access memory cell compatible with 300 mm Si CMOS technology. The demand ...